A problem in many integrated circuits is the detection of the initial power-on state. There are many functions which may be needed to perform at initial power-on such as self-testing, clearing garbage data from memory and restoring all elements to a known state and loading saved data.
This is particularly useful for battery-backed or battery operated integrated circuits, which may be used to perform power-management or nonvolatizing functions for an electronic system. If such a component has lost its battery power, it may loose its valid data, and may begin to issue erroneous commands to the system. Thus, a great many types of integrated circuits include a "power-on-reset" circuit to detect when power is applied after a power-down condition, and to issue a reset pulse, which is used to initiate performance of the above named functions.
Two objectives in selecting a power-on reset circuit is that the circuit must not generate the reset pulse when not needed, second, the circuit must generate the reset pulse when it is needed.
Particularly in the design of today's dynamic DRAM memories, latches may be employed to set the state of signals to predetermined logic levels during an active or a precharge portion of a memory cycle. The use of these latches may require a master reset signal to force the state of these signals or logic levels to known value subsequent to the DRAM memory powering up. This operation insures that the DRAM memory is properly conditioned in a low power standby state of the RAM memory while waiting for the first memory cycle to be applied to the RAM memory. An ideal operation, the master reset signal should follow the supply voltage until the supply voltage has reached a sufficient voltage level such that all the signals or logic levels can be reset, and then master reset signal should be returned to ground potential. With the emphasis today on utilizing only very low standby power from battery power backup systems, it is desirable that the circuit that produces this master reset signal consume little or no current once the device has been powered up. Furthermore, this reset signal should be generated every time the RAM memory is powered up regardless of the length of time between subsequent power-up intervals. This generation of the master reset signal regardless of the length of the interval of time insures that despite the power-up sequence of the RAM memory, the state of the RAM memory is properly set for correct and accurate memory operation.
These two requirements, namely that the standby current drain from the circuit to produce the master reset signal has been unsatisfactorily large or the circuit to produce the master reset signal requires an unacceptably long period of time to accurately reproduce the master reset signal between power-ups and downs has not been met by the prior art in one circuit.
FIG. 1 illustrates a power-up detector that provides a power-up detector signal, PUD. This circuit has the disadvantage of producing a large standby current drain from the power supply. The circuit has the following behavior as power is applied to the circuit. Initially nodes 200, 202, 204, 206 and 208 are at V.sub.ss or ground potential. As V.sub.dd rises to V.sub.tp potential, the threshold voltage of p-channel transistor 100, transistor 100 will turn on. This causes node 200 to charge toward V.sub.dd potential, forcing node 202 low due to the operation of invertor 110, node 204 high due to the action of invertor 112, node 206 low due to the action of invertor 114 and node 208, PUD, high due to the action of invertor 116, providing a signal to indicate the power-up condition.
As node 200 charges toward V.sub.dd, n-channel transistor 106 will turn on, creating a voltage divider between transistor 100 and transistor 106. Since node 206 has been set low, n-channel transistor 104 is off and transistors 108 and 104 do not conduct current at this time. Transistors 100 and 106 are designed such that the potential on node 200 will not drop below the switching threshold of inverter 110 until V.sub.dd has reached sufficient potential to assure the proper operation of all internal circuitry and the proper initialization of all internal nodes. As V.sub.dd reaches the required potential where proper initialization has been achieved, the rate of increase in the potential of node 200 is less than the rate of increase in the switching threshold of inverter 110.
Thus, the potential on node 200 drops below the switching threshold of invertor 110. Node 202 is forced high due to the operation of invertor 110, node 204 is forced low due to the operation of invertor 112, node 206 is forced high due to the operation of invertor 114 and node 208, PUD is forced low due the action of invertor 116, indicating that the power up period has ended. As node 206 goes high it turns on transistor 104. A discharging path through devices 108 and 104 is thus created that pulls node 200 close to ground, V.sub.ss, potential. This feedback path is provided to insure that node 200 does not oscillate around the switching threshold of invertor 110, due to supply noise, and cause multiple PUD signals. Because of the feedback path, there is a continuous current path from V.sub.dd to V.sub.ss while the circuit is powered on.
For example, the current may be in the 50 micro amp-range. This is a very significant contribution to the overall current of the device used with the power-up detector and as a consequence resulting in inefficiencies.
FIG. 2 illustrates a power-up detector circuit that effectively eliminates this standby current; however, it has the disadvantage that during a power-up-down-up sequence of short duration, the power-up detector circuit fails to provide a power-up detection signal on the last power-up.
The operation of FIG. 2 is as follows. Before initial power-up, node 400 is at ground, V.sub.ss, potential. As V.sub.dd rises to V.sub.tp, the threshold voltage of the p-channel transistor in invertor 308, node 402, PUD, goes high, providing a signal to indicate the power-up condition. P-channel transistor 306 is designed to have a higher threshold voltage than V.sub.tp so that it will not turn on before invertor 308 forces PUD high, thereby assuring that transistor 306 remains off. Node 400 will remain low until V.sub.dd exceeds the sum of the threshold voltage of p-channel transistor 300 and the threshold voltage of p-channel transistor 302. PUD will remain high until node 400 reaches the switching threshold of invertor 308. V.sub.dd must exceed this threshold by the sum of the thresholds of transistors 300 and 302. This voltage level is sufficient to insure the proper operation of all internal circuitry and to insure the proper initialization of all internal nodes. Once node 400 exceeds the switching threshold of invertor 308, node 402 is forced low, indicating that the power-up period has ended. When node 402 goes low, transistor 306 is turned on, pulling node 400 to V.sub.dd potential. This assures that there is no current path in invertor 308 due to an intermediate voltage level on node 400. This circuit draws no current while the device is powered on.
The circuit of FIG. 2 has the disadvantage of not detecting a second power-up sequence if it occurs too soon after a power-down. The problem can be seen from the following discussion. Recall that after power-up, node 400 was brought to V.sub.dd potential. When the device is powered down the only discharge path for node 400 is through transistor 306. Node 400 will follow the V.sub.dd supply as it is discharged until V.sub.dd reaches a potential of V.sub.tp, where V.sub.tp is the threshold voltage of p-channel transistor 306. Thus, when the V.sub.dd supply is fully discharged to ground, node 400 is still at V.sub.tp potential. The only way that node 400 can be fully discharged to ground is through junction and subthreshold leakage. These leakages are very small, requiring on the order of seconds to discharge node 400 to ground potential. If power-up is attempted before node 400 has been sufficiently discharged, the circuit will not provide a power-up detect signal. This failure is due to node 400 remaining at greater than a V.sub.tn potential, where V.sub.tn is the threshold voltage of the n-channel transistor in invertor 308. If this occurs, node 402 will be held at a low state during the second power-up sequence, improperly indicating that the power-up period has ended.